Electrostatic discharge circuit and display panel

ABSTRACT

An electrostatic discharge circuit and a display panel are provided. The electrostatic discharge circuit comprises a first discharge unit, a second discharge unit and a third discharge unit. The first discharge unit comprises a first transistor and a second transistor, and a source of the first transistor is connected to a high level terminal. The gate and drain of the first transistor and the gate and drain of the second transistor are connected to an electrostatic input terminal. A source of the second transistor is connected to a low level terminal. An input terminal of the second discharge unit is connected to the electrostatic input terminal, an output terminal of the second discharge unit is connected to a common terminal. An input terminal of the third discharge unit is connected to the electrostatic input terminal, an output terminal of the third discharge unit is connected to the common terminal.

BACKGROUND Technical Field

This disclosure relates to a technical field of a display, and moreparticularly to an electrostatic discharge circuit and a display panel.

RELATED ART

Liquid crystal display has many advantages including the thin body, thepower saving property and the radiation-free property and is widelyapplied. The existing liquid crystal displays are mainly backlightliquid crystal display which comprises a liquid crystal panel and abacklight module. The work principle of the liquid crystal display isthat the liquid crystal molecules are placed between two parallel glasssubstrates, and a drive voltage is applied to the two glass substratesto control the rotating directions of the liquid crystal molecules so asto refract the light from the backlight module to generate an image.

TFT-LCD (Thin Film Transistor-Liquid Crystal Display) has graduallyoccupied the dominant position in the display field due to its low powerconsumption, excellent image quality and high production yield.Similarly, the TFT-LCD comprises a liquid crystal panel and a backlightmodule. The liquid crystal panel comprises a CF substrate (Color FilterSubstrate) and a TFT substrate (Thin Film Transistor Substrate).Transparent electrodes are provided on opposite inner sides of thesubstrates. A layer of liquid crystal (LC) is interposed between the twosubstrates.

Electrostatic discharge (referred to as ESD) exceeding a certain voltagecan breakdown the integrated circuit chip dielectrics, fuse the corewire, increase the leakage current to accelerate aging, and change theelectrical performance parameters and so on. Therefore, ESD protectionis quite important.

SUMMARY

The technical problem to be solved by this disclosure is to provide anelectrostatic discharge circuit having a reliable and effectiveprotection circuit.

In addition, this disclosure further provides a display panel comprisingthe above-mentioned electrostatic discharge circuit.

The objective of this disclosure is achieved through the followingtechnical solutions:

An electrostatic discharge circuit, comprising a first discharge unit, asecond discharge unit and a third discharge unit. The first dischargeunit comprises a first transistor and a second transistor. A source ofthe first transistor is connected to a high level terminal. A gate and adrain of the first transistor are connected together to form a firstpole. A gate and a drain of the second transistor are connected togetherto form a second pole. The first pole and the second pole are connectedtogether and connected to an electrostatic input terminal. A source ofthe second transistor is connected to a low level terminal. An inputterminal of the second discharge unit is connected to the electrostaticinput terminal. An output terminal of the second discharge unit isconnected to a common terminal. An input terminal of the third dischargeunit is connected to the electrostatic input terminal. An outputterminal of the third discharge unit is connected to the commonterminal.

In one embodiment, the second discharge unit comprises a firstelectroconductive wire having one end connected to the common terminal,and the common terminal is grounded; or the second discharge unitcomprises a first electroconductive wire having one end connected to thecommon terminal, the electrostatic discharge circuit is disposed on adisplay panel, and the common terminal is connected to a common voltageterminal of the display panel. The required line width of theelectroconductive wire used between the high level terminal (VGH) andthe low level terminal (VGL) is small. This is equivalent to a largerresistance, the discharge current is also relatively smaller, and thedischarge ability provided by the first discharge unit alone may not besufficient. However, the first electroconductive wire is connected tothe ground (GND). Alternatively, the first electroconductive wire isconnected to the common voltage terminal (VCOM), and its line width isfar greater than the line widths of the VGH and VGL, so the current thatcan be discharged will be higher than the original current so as toachieve a better protective effect.

In one embodiment, the third discharge unit comprises a secondelectroconductive wire having one end connected to the common terminal,and the common terminal is grounded; or the third discharge unitcomprises a second electroconductive wire having one end connected tothe common terminal, and the common terminal is connected to a commonvoltage terminal of the display panel. The required line width of theelectroconductive wire used between the high level terminal (VGH) andthe low level terminal (VGL) is small. This is equivalent to a largerresistance, the discharge current is also relatively smaller, and thedischarge ability provided by the first discharge unit alone may not besufficient. However, the first electroconductive wire is connected tothe ground (GND). Alternatively, the first electroconductive wire isconnected to the common voltage terminal (VCOM), and its line width isfar greater than the line widths of the VGH and VGL, so the current thatcan be discharged will be higher than the original current so as toachieve a better protective effect.

In one embodiment, the second discharge unit comprises a thirdtransistor, and an input terminal and a control terminal of the thirdtransistor are connected to the electrostatic input terminal, and anoutput terminal of the third transistor is connected to the commonterminal. The third discharge unit comprises a fourth transistor, and aninput terminal and a control terminal of the fourth transistor areconnected to the electrostatic input terminal, and an output terminal ofthe fourth transistor is connected to the common terminal. The seconddischarge unit discharges through the third transistor, and theconfiguration is simple, effective and reliable. The third dischargeunit discharges through the fourth transistor, and the configuration issimple, effective and reliable.

In one embodiment, the second discharge unit comprises a firstcapacitor, and a first terminal of the first capacitor is connected tothe electrostatic input terminal, and a second terminal of the firstcapacitor is connected to the control terminal of the third transistor.The third discharge unit comprises a second capacitor, and a firstterminal of the second capacitor is connected to the electrostatic inputterminal, and a second terminal of the second capacitor is connected tothe control terminal of the fourth transistor. According to theproperties that the capacitor can block the DC, conduct the AC, conductthe high frequency and block the low frequency, when the voltage rangeis from VGL to VGH, the second discharge unit and the third dischargeunit do not work. At the same time, when the voltage range is not fromVGL to VGH, for example, when there is applied with a positive highvoltage instantaneously, the second discharge unit can work normally,and does not generate the current of VGL left through the secondtransistor. For example, when there is applied with a negative highvoltage instantaneously, the third discharge unit can work normally.

In one embodiment, the second discharge unit comprises a fifthtransistor, and an input terminal of the fifth transistor is connectedto the second terminal of the first capacitor, a control terminal of thefifth transistor is connected to the high level terminal, and an outputterminal of the fifth transistor is connected to the low level terminal.The third discharge unit comprises a sixth transistor, and an inputterminal of the sixth transistor is connected to the second terminal ofthe second capacitor, a control terminal of the sixth transistor isconnected to the low level terminal, and an output terminal of the sixthtransistor is connected to the high level terminal. At the positivevoltage, the fifth transistor, which is turned on, further completes thedischarge function of the second discharge unit, and the potential ofthe second terminal of the first capacitor is pulled to be consistentwith the common terminal at the same time. In this manner, when thevoltage range is from VGL to VGH, the third transistor cannot be turnedon to discharge and affect the normal work of the protection circuit. Atthe negative voltage, the sixth transistor, which is turned on, furthercompletes the discharge function of the third discharge unit, and thepotential of the second terminal of the second capacitor is pulled to beconsistent with the common terminal at the same time. In this manner,when the voltage range is from VGL to VGH, the fourth transistor cannotbe turned on to discharge and affect the normal work of the protectioncircuit.

In one embodiment, the first transistor is a first N-type transistor,the second transistor is a second P-type transistor, the thirdtransistor is a third N-type transistor, the fourth transistor is afourth P-type transistor, the fifth transistor is a fifth N-typetransistor, and the sixth transistor is a sixth P-type transistor. Hereshows an implementation aspect of the electrostatic discharge circuit,clearly and specifically adopted electrical components and connectionrelationships.

In one embodiment, the first transistor is a first N-type transistor,the second transistor is a second P-type transistor, the thirdtransistor is a third P-type transistor, the fourth transistor is afourth N-type transistor, the fifth transistor is a fifth N-typetransistor, and the sixth transistor is a sixth P-type transistor. Hereshows an implementation aspect of the electrostatic discharge circuit,clearly and specifically adopted electrical components and connectionrelationships.

According to another aspect of this disclosure, this disclosure furtherprovide an electrostatic discharge circuit. The electrostatic dischargecircuit comprises a first discharge unit, a second discharge unit and athird discharge unit. The first discharge unit comprises a first N-typetransistor and a second P-type transistor. A source of the first N-typetransistor is connected to a high level terminal. A gate and a drain ofthe first N-type transistor are connected together to form a first pole.A gate and a drain of the second P-type transistor are connectedtogether to form a second pole. The first pole and the second pole areconnected together and connected to an electrostatic input terminal. Asource of the second P-type transistor is connected to a low levelterminal. The second discharge unit comprises a third N-type transistor,a first capacitor, and a fifth N-type transistor. A source of the thirdN-type transistor is connected to the gate of the first N-typetransistor. A drain of the third N-type transistor is connected to acommon terminal, the common terminal is grounded. A first terminal ofthe first capacitor is connected to the electrostatic input terminal. Asecond terminal of the first capacitor is connected to a gate of thethird N-type transistor. A source of the fifth N-type transistor isconnected to the second terminal of the first capacitor. A gate of thefifth N-type transistor is connected to the high level terminal. A drainof the fifth N-type transistor is connected to the low level terminal,and the second discharge unit functions to discharge when a positivevoltage is applied. The third discharge unit comprises a fourth P-typetransistor, a second capacitor and a sixth P-type transistor. A sourceof the fourth P-type transistor is connected to the gate of the secondP-type transistor. A drain of the fourth P-type transistor is connectedto the common terminal, the common terminal is grounded. A firstterminal of the second capacitor is connected to the electrostatic inputterminal. A second terminal of the second capacitor is connected to agate of the fourth P-type transistor. A source of the sixth P-typetransistor is connected to the second terminal of the second capacitor.A gate of the sixth P-type transistor is connected to the low levelterminal. A drain of the sixth P-type transistor is connected to thehigh level terminal, and the third discharge unit functions to dischargewhen a negative voltage is applied.

According to still another aspect of this disclosure, this disclosurefurther provide a display panel. The display panel comprises asubstrate, signal lines and the electrostatic discharge circuit. Anactive switch is disposed on the substrate. The signal lines aredisposed on the substrate and coupled to the active switch, and thesignal lines comprise multiple scan lines and multiple data lines, andthe multiple data lines and the multiple scan lines successivelyintersect to form multiple pixel areas. The electrostatic dischargecircuit is disposed on the substrate.

In one embodiment, the display panel further comprises a gate drivecircuit and a source drive circuit, which are disposed on the substrate.

In this disclosure, because the second discharge unit and the thirddischarge unit are connected to and cooperate with the first dischargeunit, no matter whether there is a positive or negative high voltageinstantaneously applied to the electrostatic input, respectivelycooperating with the second discharge unit and the third discharge unitoutside the first discharge unit can increase the ESD discharge currentpath, so that the speed and amount of discharge can be increased, abetter protection effect on the display panel is achieved, and thelifetime is extended.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments of the present application, whichconstitutes a part of the specification, illustrate embodiments of thepresent disclosure is used, together and explain the principles of thepresent disclosure with the description. Apparently, the drawings in thefollowing description are only some embodiments of the presentdisclosure, those of ordinary skill in the art is concerned, without anycreative effort, and may also obtain other drawings based on thesedrawings. In the drawings:

FIG. 1 is a schematic view showing an electrostatic discharge circuit ofa display panel of the embodiment of this disclosure;

FIG. 2 is a schematic view showing an electrostatic discharge circuit ofa display panel of the embodiment of this disclosure;

FIG. 3 is a schematic view showing an electrostatic discharge circuit ofa display panel of the embodiment of this disclosure;

FIG. 4 is a schematic view showing an electrostatic discharge circuit ofa display panel of the embodiment of this disclosure;

FIG. 5 is a schematic structure view showing a display panel of theembodiment of this disclosure; and

FIG. 6 is a schematic structure view showing a display device of theembodiment of this disclosure.

DETAILED DESCRIPTION OF THE INVENTION

Specific structural and functional details disclosed herein are merelyrepresentative and are for purposes of describing example embodiments ofthe present invention. However, the present invention may be embodied inmany alternate forms, and should not be interpreted as being limited tothe embodiments set forth herein.

In the description of the present invention, it is to be understood thatthe term “center”, “lateral”, “upper”, “lower”, “left”, “right”,“vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and otherindicated orientation or positional relationships are based on thelocation or position relationship shown in the drawings, and are forconvenience of description of the present invention only and to simplifythe description, and not indicate or imply that refers to devices orelements must have a specific orientation, the orientation of aparticular configuration and operation, therefore, cannot be construedas limiting the present invention. In addition, the terms “first”,“second” are used to indicate or imply relative importance or the numberof technical features specified implicitly indicated the purpose ofdescription and should not be understood. Thus, there is defined“first”, “second” features may be explicitly or implicitly include oneor more of the features. In the description of the present invention,unless otherwise specified, the meaning of “more” is two or more.Further, the term “comprising” and any variations thereof, are intendedto cover non-exclusive inclusion.

In the description of the present invention, it is noted that, unlessotherwise expressly specified or limited, the terms “mounted,”“connected to”, “connected” are to be broadly understood, for example,may be a fixed connection, may be a detachable connection, or integrallyconnected; may be a mechanical connector may be electrically connected;may be directly connected, can also be connected indirectly throughintervening structures, it may be in communication the interior of thetwo elements. Those of ordinary skill in the art, be appreciated thatthe specific circumstances of the specific meanings in the presentinvention.

The terminology used herein is for describing particular embodimentsonly and is not intended to limit embodiments to an exemplaryembodiment. Unless the context clearly indicates otherwise, singularforms as used herein, “a”, “an” are intended to include the plural. Itshould also be understood that, as used herein the term “comprising”and/or “comprising,” as used herein, specify the presence of statedfeatures, integers, steps, operations, elements, and/or components, butdo not preclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or combinationsthereof.

This disclosure will be further described in detail with reference tothe accompanying drawings and specific embodiments below.

A schematic view of an electrostatic discharge circuit of the embodimentof this disclosure will be described below with reference to FIGS. 1 to4.

As an embodiment of this disclosure, as shown in FIG. 1, anelectrostatic discharge circuit 11 comprises a first discharge unit, asecond discharge unit 6 and a third discharge unit 7. The firstdischarge unit comprises a first transistor and a second transistor, asource of the first transistor is connected to a high level terminal, agate and a drain of the first transistor are connected together to forma first pole, a gate and a drain of the second transistor are connectedtogether to form a second pole, the first pole and the second pole areconnected together and connected to an electrostatic input terminal 4,and a source of the second transistor is connected to a low levelterminal; an input terminal of the second discharge unit 6 is connectedto the electrostatic input terminal 4, and an output terminal of thesecond discharge unit 6 is connected to a common terminal 3; and aninput terminal of the third discharge unit 7 is connected to theelectrostatic input terminal 4, and an output terminal of the thirddischarge unit 7 is connected to the common terminal 3. The seconddischarge unit 6 and the third discharge unit 7 are connected to andcooperate with the first discharge unit, no matter whether there is apositive or negative high voltage instantaneously applied to theelectrostatic input 4, respectively cooperating with the seconddischarge unit 6 and the third discharge unit 7 outside the firstdischarge unit can increase the ESD discharge current path, so that thespeed and amount of discharge can be increased, a better protectioneffect on the display panel is achieved, and the lifetime is extended.As shown in FIG. 5, the display panel comprises a substrate 10, signallines and the electrostatic discharge circuit 11. An active switch isdisposed on the substrate 10; the signal lines are disposed on thesubstrate 10 and coupled to the active switch, the signal lines comprisemultiple scan lines 14 and multiple data lines 15, and the multiple datalines 15 and the multiple scan lines 14 successively intersect to formmultiple pixel areas 16; the electrostatic discharge circuit 11, a gatedrive circuit 12 and a source drive circuit 13 are disposed on thesubstrate 10, the horizontal disposed scan lines 14 and the verticaldisposed data lines 15 are coupled and connected to their correspondingcircuits, and the active switch may be, for example, a thin filmtransistor. The high level terminal, the low level terminal, theelectrostatic input terminal 4 and the common terminal 3 are coupled tocomponents of the display panel.

Specifically, the second discharge unit 6 comprises a firstelectroconductive wire having one end connected to the common terminal3, and the common terminal 3 is grounded; alternatively, the seconddischarge unit 6 comprises a first electroconductive wire having one endconnected to the common terminal 3, and the common terminal 3 isconnected to a common voltage terminal of the display panel. Therequired line width of the electroconductive wire used between the highlevel terminal (VGH) 1 and the low level terminal (VGL) 2 is small. Thisis equivalent to a larger resistance, the discharge current is alsorelatively smaller, and the discharge ability provided by the firstdischarge unit alone may not be sufficient. However, the firstelectroconductive wire is connected to the ground (GND). Alternatively,the first electroconductive wire is connected to the common voltageterminal (VCOM), and its line width is far greater than the line widthsof the VGH and VGL, so the current that can be discharged will be higherthan the original current so as to achieve a better protective effect.The third discharge unit 7 comprises a second electroconductive wirehaving one end connected to the common terminal 3, and the commonterminal 3 is grounded; alternatively, the third discharge unit 7comprises a second electroconductive wire having one end connected tothe common terminal 3, and the common terminal 3 is connected to thecommon voltage terminal of the display panel. However, the secondelectroconductive wire is connected to the ground (GND). Alternatively,the second electroconductive wire is connected to the common voltageterminal (VCOM), and its line width is far greater than the line widthsof the VGH and VGL, so the current that can be discharged will be higherthan the original current so as to achieve a better protective effect.The display panel comprises a gate integrated circuit, a high levelterminal, a low level terminal connected to a transistor turn-on voltageterminal and a transistor turn-off voltage terminal of the gateintegrated circuit, respectively.

As one embodiment of this disclosure, an electrostatic discharge circuit11 comprises a first discharge unit, a second discharge unit 6 and athird discharge unit 7. The first discharge unit comprises a firsttransistor and a second transistor, a source of the first transistor isconnected to a high level terminal, a gate and a drain of the firsttransistor are connected together to form a first pole, a gate and adrain of the second transistor are connected together to form a secondpole, the first pole and the second pole are connected together andconnected to an electrostatic input terminal 4, and a source of thesecond transistor is connected to a low level terminal; an inputterminal of the second discharge unit 6 is connected to theelectrostatic input terminal 4, and an output terminal of the seconddischarge unit 6 is connected to a common terminal 3; and an inputterminal of the third discharge unit 7 is connected to the electrostaticinput terminal 4, and an output terminal of the third discharge unit 7is connected to the common terminal 3. The second discharge unit 6 andthe third discharge unit 7 are connected to and cooperate with the firstdischarge unit, no matter whether there is a positive or negative highvoltage instantaneously applied to the electrostatic input 4,respectively cooperating with the second discharge unit 6 and the thirddischarge unit 7 outside the first discharge unit can increase the ESDdischarge current path, so that the speed and amount of discharge can beincreased, a better protection effect on the display panel is achieved,and the lifetime is extended. The second discharge unit 6 comprises athird transistor and a first capacitor 63, and an input terminal and acontrol terminal of the third transistor are connected to theelectrostatic input terminal 4, and an output terminal of the thirdtransistor is connected to the common terminal 3. A first terminal of afirst capacitor 63 is connected to the electrostatic input terminal 4,and a second terminal of the first capacitor 63 is connected to thecontrol terminal of the third transistor. The third discharge unit 7comprises a fourth transistor and a second capacitor 73, and an inputterminal and a control terminal of the fourth transistor are connectedto the electrostatic input terminal 4, and an output terminal of thefourth transistor is connected to the common terminal 3. A firstterminal of a second capacitor 73 is connected to the electrostaticinput terminal 4, and a second terminal of the second capacitor 73 isconnected to the control terminal of the fourth transistor. The seconddischarge unit 6 and the third discharge unit 7 respectively dischargethrough the third transistor and the fourth transistor, and theconfiguration is simple, effective and reliable. According to theproperties that the capacitor can block the DC, conduct the AC, conductthe high frequency and block the low frequency, when the voltage rangeis from VGL to VGH, the second discharge unit 6 and the third dischargeunit 7 do not work. At the same time, when the voltage range is not fromVGL to VGH, for example, when there is applied with a positive highvoltage instantaneously, the second discharge unit 6 can work normally,and does not generate the current of VGL left through the secondtransistor. For example, when there is applied with a negative highvoltage instantaneously, the third discharge unit 7 can work normally.So, if the input voltage range of the PIN ranges from VGL to VGH, thiscapacitor and transistor do not operate because the capacitor in the DCcurrent can be considered as an open circuit.

Specifically, as shown in FIG. 2, a first discharge unit comprises afirst N-type transistor 51 and a second P-type transistor 52, and asource of the first N-type transistor 51 is connected to a high levelterminal, a gate and a drain of the first N-type transistor 51 areconnected together to form a first pole, a gate and a drain of thesecond P-type transistor 52 are connected together to form a secondpole, the first pole and the second pole are connected together andconnected to an electrostatic input terminal 4, and a source of thesecond P-type transistor 52 is connected to a low level terminal. Asource of a third N-type transistor 61 is connected to a gate of a firstN-type transistor 51, a drain of the third N-type transistor 61 isconnected to the common terminal 3, the common terminal 3 is grounded, afirst terminal of a first capacitor 63 is connected to the electrostaticinput terminal 4, and a second terminal of the first capacitor 63 isconnected to a gate of the third N-type transistor 61. A source of afourth P-type transistor 71 is connected to a gate of a second P-typetransistor 52, a drain of the fourth P-type transistor 71 is connectedto the common terminal 3, the common terminal 3 is grounded, a firstterminal of a second capacitor 73 is connected to the electrostaticinput terminal 4, and a second terminal of the second capacitor 73 isconnected to a gate of the fourth P-type transistor 71. When there is apositive high voltage instantaneously applied to the PIN, the firstN-type transistor 51 is turned on, and a first discharge current 81 isgenerated. Because the PIN potential instantaneously becomes high, thepotential of the point connected between the second terminal of thefirst capacitor 63 and the gate of the third N-type transistor 61 alsobecomes high at the same time under capacitive coupling special effects,and the third N-type transistor 61 is also turned on. At this time, thepositive high voltage of the PIN can be discharged to GND. Because theGND trace is usually thicker than VGL, the corresponding resistancevalue is much smaller than VGL, so a second discharge current 82 ishigher than the first discharge current 81. When there is a negativehigh voltage instantaneously applied to the PIN, the second P-typetransistor 52 is turned on, and a fourth discharge current 91 isgenerated. Because the PIN potential instantaneously becomes negative,the second terminal of the second capacitor 73 also becomes negative atthe same time under capacitive coupling special effects, the fourthP-type transistor 71 is also turned on, and a fifth discharge current 92is generated. At this time, the negative high voltage of the PIN can bedischarged to GND. Because the GND trace is usually thicker than VGL,the corresponding resistance value is much smaller than VGL, so thefifth discharge current 92 is higher than the fourth discharge current91.

As another embodiment of this disclosure, an electrostatic dischargecircuit 11 comprises a first discharge unit, a second discharge unit 6and a third discharge unit 7. The first discharge unit comprises a firsttransistor and a second transistor, a source of the first transistor isconnected to a high level terminal, a gate and a drain of the firsttransistor are connected together to form a first pole, a gate and adrain of the second transistor are connected together to form a secondpole, the first pole and the second pole are connected together andconnected to an electrostatic input terminal 4, and a source of thesecond transistor is connected to a low level terminal. An inputterminal of the second discharge unit 6 is connected to theelectrostatic input terminal 4, and an output terminal of the seconddischarge unit 6 is connected to a common terminal 3; and an inputterminal of the third discharge unit 7 is connected to the electrostaticinput terminal 4, and an output terminal of the third discharge unit 7is connected to the common terminal 3. The second discharge unit 6 andthe third discharge unit 7 are connected to and cooperate with the firstdischarge unit, no matter whether there is a positive or negative highvoltage instantaneously applied to the electrostatic input 4,respectively cooperating with the second discharge unit 6 and the thirddischarge unit 7 outside the first discharge unit can increase the ESDdischarge current path, so that the speed and amount of discharge can beincreased, a better protection effect on the display panel is achieved,and the lifetime is extended. The second discharge unit 6 comprises athird transistor, a first capacitor 63 and a fifth transistor, and aninput terminal and a control terminal of the third transistor areconnected to the electrostatic input terminal 4, and an output terminalof the third transistor is connected to the common terminal 3; the firstterminal of the first capacitor 63 is connected to the electrostaticinput terminal 4, and the second terminal of the first capacitor 63 isconnected to a control terminal of third transistor; an input terminalof the fifth transistor is connected to the second terminal of the firstcapacitor 63, the control terminal of the fifth transistor is connectedto the high level terminal, and an output terminal of the fifthtransistor is connected to the low level terminal; the third dischargeunit 7 comprises a fourth transistor, a second capacitor 73 and a sixthtransistor, and an input terminal and a control terminal of the fourthtransistor are connected to the electrostatic input terminal 4, and anoutput terminal of the fourth transistor is connected to the commonterminal 3; the first terminal of the second capacitor 73 is connectedto the electrostatic input terminal 4, and the second terminal of thesecond capacitor 73 is connected to the control terminal of the fourthtransistor; and an input terminal of the sixth transistor is connectedto the second terminal of the second capacitor 73, the control terminalof the sixth transistor is connected to the low level terminal, and anoutput terminal of the sixth transistor is connected to the high levelterminal.

The second discharge unit 6 and the third discharge unit 7 respectivelydischarge through the third transistor and the fourth transistor, andthe configuration is simple, effective and reliable. According to theproperties that the capacitor can block the DC, conduct the AC, conductthe high frequency and block the low frequency, when the voltage rangeis from VGL to VGH, the second discharge unit 6 and the third dischargeunit 7 do not work. At the same time, when the voltage range is not fromVGL to VGH, for example, when there is applied with a positive highvoltage instantaneously, the second discharge unit 6 can work normally,and does not generate the current of VGL left through the secondtransistor. For example, when there is applied with a negative highvoltage instantaneously, the third discharge unit 7 can work normally.So, if the input voltage range of the PIN ranges from VGL to VGH, thiscapacitor and transistor do not operate because the capacitor in the DCcurrent can be considered as an open circuit. At the positive voltage,the fifth transistor, which is turned on, further completes thedischarge function of the second discharge unit 6, and the potential ofthe second terminal of the first capacitor 63 is pulled to be consistentwith the common terminal 3 at the same time. In this manner, when thevoltage range is from VGL to VGH, the third transistor cannot be turnedon to discharge and affect the normal work of the protection circuit. Atthe negative voltage, the sixth transistor, which is turned on, furthercompletes the discharge function of the second discharge unit 7, and thepotential of the second terminal of the first capacitor 73 is pulled tobe consistent with the common terminal 3 at the same time. In thismanner, when the voltage range is from VGL to VGH, the fourth transistorcannot be turned on to discharge and affect the normal work of theprotection circuit.

Specifically, as shown in FIGS. 3 and 4, and FIG. 4 can be looked as theactual equivalent circuit of FIG. 3, the first discharge unit comprisesa first N-type transistor 51 and a second P-type transistor 52, and asource of the first N-type transistor 51 is connected to the high levelterminal, a gate and a drain of the first N-type transistor 51 areconnected together to form a first pole, a gate and a drain of thesecond P-type transistor 52 are connected together to form a secondpole, the first pole and the second pole are connected together andconnected to the electrostatic input terminal 4, and a source of thesecond P-type transistor 52 is connected to the low level terminal. Thesecond discharge unit 6 comprises a third N-type transistor 61, a firstcapacitor 63 and a fifth N-type transistor 62, and a source of the thirdN-type transistor 61 is connected to the gate of the first N-typetransistor 51, a drain of the third N-type transistor 61 is connected tothe common terminal 3, the common terminal 3 is grounded, the firstterminal of the first capacitor 63 is connected to the electrostaticinput terminal 4, the second terminal of the first capacitor 63 isconnected to a gate of the third N-type transistor 61, a source of thefifth N-type transistor 62 is connected to the second terminal of thefirst capacitor 63, a gate of the fifth N-type transistor 62 isconnected to the high level terminal, and a drain of the fifth N-typetransistor 62 is connected to the low level terminal. The thirddischarge unit 7 comprises a fourth P-type transistor 71, a secondcapacitor 73 and a sixth P-type transistor 72, and a source of thefourth P-type transistor 71 is connected to the gate of the secondP-type transistor 52, a drain of the fourth P-type transistor 71 isconnected to the common terminal 3, the common terminal 3 is grounded,the first terminal of the second capacitor 73 is connected to theelectrostatic input terminal 4, the second terminal of the secondcapacitor 73 is connected to a gate of the fourth P-type transistor 71,a source of the sixth P-type transistor 72 is connected to the secondterminal of the second capacitor 73, a gate of the sixth P-typetransistor 72 is connected to the low level terminal, and a drain of thesixth P-type transistor 72 is connected to the high level terminal.Because the PIN potential instantaneously becomes high, the potential ofthe point connected between the second terminal of the capacitor and thegate of the third N-type transistor 61 also becomes high at the sametime under capacitive coupling special effects, and the third N-typetransistor 61 is also turned on. At this time, the positive high voltageof the PIN can be discharged to GND. Because the GND trace is usuallythicker than VGL, the corresponding resistance value is much smallerthan VGL, so the second discharge current 82 is higher than the firstdischarge current 81. However, the fifth N-type transistor 62 also pullsthe potential of the point connected between the second terminal of thefirst capacitor 63 and the gate of the third N-type transistor 61 to GNDat the same time. So, when there is a large positive voltageinstantaneously applied to the PIN, the discharged current is the sum ofthe first discharge current 81, the second discharge current 82 and athird discharge current 83, which is also higher, and is higher than thetotal discharge current generated when the first discharge unit solelyacts, to have a better protection effect. Because the PIN potentialinstantaneously becomes negative, the second terminal of the secondcapacitor 73 also becomes negative at the same time under capacitivecoupling special effects, the fourth P-type transistor 71 is also turnedon, and the fifth discharge current 92 is generated. At this time, thenegative high voltage of the PIN can be discharged to GND. Because theGND trace is usually thicker than VGL, the corresponding resistancevalue is much smaller than VGL, so the fifth discharge current 92 ishigher than the fourth discharge current 91. However, the sixth P-typetransistor 72 may also be turned on at the same time, the firstdischarge current 81 is generated, and then the second terminal of thesecond capacitor 73 is pulled to the VGH. So, when there is a largenegative voltage instantaneously applied to the PIN, the dischargedcurrent is the sum of the fourth discharge current 91, the fifthdischarge current 92 and a sixth discharge current 93, which is alsohigher, and is higher than the total discharge current generated whenthe first discharge unit solely acts, to have a better protectioneffect.

Of course, the second discharge unit 6 and the third discharge unit 7may also be configured as follows. The second discharge unit 6 comprisesa third N-type transistor, a first capacitor 63 and a fifth N-typetransistor 62, and a source of the third N-type transistor is connectedto the gate of the first N-type transistor 51, a drain of the thirdN-type transistor is connected to the common terminal 3, the commonterminal 3 is grounded, the first terminal of the first capacitor 63 isconnected to the electrostatic input terminal 4, the second terminal ofthe first capacitor 63 is connected to a gate of the third N-typetransistor 61, a source of the fifth N-type transistor 62 is connectedto the second terminal of the first capacitor 63, a gate of the fifthN-type transistor 62 is connected to the high level terminal, and adrain of the fifth N-type transistor 62 is connected to the low levelterminal. The third discharge unit 7 comprises a fourth N-typetransistor, a second capacitor 73 and a sixth P-type transistor 72, anda source of the fourth N-type transistor is connected to the gate of thesecond P-type transistor 52, a drain of the fourth N-type transistor isconnected to the common terminal 3, the common terminal 3 is grounded,the first terminal of the second capacitor 73 is connected to theelectrostatic input terminal 4, the second terminal of the secondcapacitor 73 is connected to a gate of the fourth N-type transistor 71,a source of the sixth P-type transistor 72 is connected to the secondterminal of the second capacitor 73, a gate of the sixth P-typetransistor 72 is connected to the low level terminal, and a drain of thesixth P-type transistor 72 is connected to the high level terminal.

It should be noted that, in the above embodiments, material of thesubstrate 10 can be selected from the group consisting of glass, plasticand the likes.

In the above embodiments, the display panel comprises a liquid crystalpanel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum DotLight Emitting Diodes) panel, a curved panel, a plasma panel and thelikes. Taking a liquid crystal panel as an example, the liquid crystalpanel comprises a TFT substrate (Thin Film Transistor Substrate) and aCF substrate (Color Filter Substrate). The TFT substrate is disposedopposite to the CF substrate, and liquid crystal and a photo spacer (PS)are disposed between the TFT substrate and the CF substrate. A thin filmtransistor (TFT) is disposed at the TFT substrate, and a color filterlayer is disposed at the CF substrate.

In the above embodiments, the CF substrate can comprise a TFT array. Thecolor filter and the TFT array can be formed on the same substrate 10.The TFT substrate can comprise color filter layer.

In the above embodiments, the display panel of this disclosure can be acurved panel.

Referring to FIG. 6, this implementation method discloses a displaydevice 30. The display device 30 comprises a control component 31, and adisplay panel 32 of this disclosure, and the display panel is taken asan example to be described in detail hereinabove. It is to be describedthat the above-mentioned description of the display panel structure isalso applicable to the display device in the embodiment of thisdisclosure. When the display device of the embodiment of this disclosureis a liquid crystal display, the liquid crystal display comprises abacklight module, and the backlight module serves as a light source forsupplying the light source with the adequate brightness and uniformdistribution. The backlight module of this embodiment may pertain to afront lighting type, and may also pertain to a backlight type. It is tobe described that the backlight module of this embodiment is not limitedthereto.

The above contents with the specific embodiments of the presentinvention is further made to the detailed description, and specificembodiments of the present invention should not be considered limited tothese descriptions. Those of ordinary skill in the art for the presentinvention, without departing from the spirit of the present invention,can make various simple deduction or replacement, and should be deemedto belong to the scope of the present invention.

What is claimed is:
 1. An electrostatic discharge circuit, comprising: afirst discharge unit comprising a first transistor and a secondtransistor, wherein a source of the first transistor is connected to ahigh level terminal, a gate and a drain of the first transistor areconnected together to form a first pole, a gate and a drain of thesecond transistor are connected together to form a second pole, thefirst pole and the second pole are connected together and connected toan electrostatic input terminal, and a source of the second transistoris connected to a low level terminal; a second discharge unit, whereinan input terminal of the second discharge unit is connected to theelectrostatic input terminal, an output terminal of the second dischargeunit is connected to a common terminal, and the second discharge unitfunctions to discharge when a positive voltage is applied; and a thirddischarge unit, wherein an input terminal of the third discharge unit isconnected to the electrostatic input terminal, an output terminal of thethird discharge unit is connected to the common terminal, and the thirddischarge unit functions to discharge when a negative voltage isapplied.
 2. The electrostatic discharge circuit according to claim 1,wherein the second discharge unit comprises a first electroconductivewire having one end connected to the common terminal, and the commonterminal is grounded; or the second discharge unit comprises a firstelectroconductive wire having one end connected to the common terminal,the electrostatic discharge circuit is disposed on a display panel, andthe common terminal is connected to a common voltage terminal of thedisplay panel.
 3. The electrostatic discharge circuit according to claim1, wherein the third discharge unit comprises a second electroconductivewire having one end connected to the common terminal, and the commonterminal is grounded; or the third discharge unit comprises a secondelectroconductive wire having one end connected to the common terminal,and the common terminal is connected to a common voltage terminal of thedisplay panel.
 4. The electrostatic discharge circuit according to claim1, wherein: the second discharge unit comprises a third transistor,wherein an input terminal and a control terminal of the third transistorare connected to the electrostatic input terminal, and an outputterminal of the third transistor is connected to the common terminal;and the third discharge unit comprises a fourth transistor, wherein aninput terminal and a control terminal of the fourth transistor areconnected to the electrostatic input terminal, and an output terminal ofthe fourth transistor is connected to the common terminal.
 5. Theelectrostatic discharge circuit according to claim 4, wherein: thesecond discharge unit comprises a first capacitor, wherein a firstterminal of the first capacitor is connected to the electrostatic inputterminal, and a second terminal of the first capacitor is connected tothe control terminal of the third transistor; and the third dischargeunit comprises a second capacitor, wherein a first terminal of thesecond capacitor is connected to the electrostatic input terminal, and asecond terminal of the second capacitor is connected to the controlterminal of the fourth transistor.
 6. The electrostatic dischargecircuit according to claim 5, wherein: the second discharge unitcomprises a fifth transistor, wherein an input terminal of the fifthtransistor is connected to the second terminal of the first capacitor, acontrol terminal of the fifth transistor is connected to the high levelterminal, and an output terminal of the fifth transistor is connected tothe low level terminal; and the third discharge unit comprises a sixthtransistor, wherein an input terminal of the sixth transistor isconnected to the second terminal of the second capacitor, a controlterminal of the sixth transistor is connected to the low level terminal,and an output terminal of the sixth transistor is connected to the highlevel terminal.
 7. The electrostatic discharge circuit according toclaim 6, wherein the first transistor is a first N-type transistor, thesecond transistor is a second P-type transistor, the third transistor isa third N-type transistor, the fourth transistor is a fourth P-typetransistor, the fifth transistor is a fifth N-type transistor, and thesixth transistor is a sixth P-type transistor.
 8. The electrostaticdischarge circuit according to claim 6, wherein the first transistor isa first N-type transistor, the second transistor is a second P-typetransistor, the third transistor is a third P-type transistor, thefourth transistor is a fourth N-type transistor, the fifth transistor isa fifth N-type transistor, and the sixth transistor is a sixth P-typetransistor.
 9. A display panel, comprising: a substrate, wherein anactive switch is disposed on the substrate; signal lines, which aredisposed on the substrate and coupled to the active switch, wherein thesignal lines comprise multiple scan lines and multiple data lines, andthe multiple data lines and the multiple scan lines successivelyintersect to form multiple pixel areas; and the electrostatic dischargecircuit according to claim 1; wherein the electrostatic dischargecircuit is disposed on the substrate.
 10. The display panel according toclaim 9, further comprising: a gate drive circuit and a source drivecircuit, which are disposed on the substrate.
 11. The electrostaticdischarge circuit according to claim 9, wherein the second dischargeunit comprises a first electroconductive wire having one end connectedto the common terminal, and the common terminal is grounded; or thesecond discharge unit comprises a first electroconductive wire havingone end connected to the common terminal, the electrostatic dischargecircuit is disposed on a display panel, and the common terminal isconnected to a common voltage terminal of the display panel.
 12. Theelectrostatic discharge circuit according to claim 9, wherein the thirddischarge unit comprises a second electroconductive wire having one endconnected to the common terminal, and the common terminal is grounded;or the third discharge unit comprises a second electroconductive wirehaving one end connected to the common terminal, and the common terminalis connected to a common voltage terminal of the display panel.
 13. Theelectrostatic discharge circuit according to claim 9, wherein: thesecond discharge unit comprises a third transistor, wherein an inputterminal and a control terminal of the third transistor are connected tothe electrostatic input terminal, and an output terminal of the thirdtransistor is connected to the common terminal; and the third dischargeunit comprises a fourth transistor, wherein an input terminal and acontrol terminal of the fourth transistor are connected to theelectrostatic input terminal, and an output terminal of the fourthtransistor is connected to the common terminal.
 14. The electrostaticdischarge circuit according to claim 13, wherein: the second dischargeunit comprises a first capacitor, wherein a first terminal of the firstcapacitor is connected to the electrostatic input terminal, and a secondterminal of the first capacitor is connected to the control terminal ofthe third transistor; and the third discharge unit comprises a secondcapacitor, wherein a first terminal of the second capacitor is connectedto the electrostatic input terminal, and a second terminal of the secondcapacitor is connected to the control terminal of the fourth transistor.15. The electrostatic discharge circuit according to claim 14, wherein:the second discharge unit comprises a fifth transistor, wherein an inputterminal of the fifth transistor is connected to the second terminal ofthe first capacitor, a control terminal of the fifth transistor isconnected to the high level terminal, and an output terminal of thefifth transistor is connected to the low level terminal; and the thirddischarge unit comprises a sixth transistor, wherein an input terminalof the sixth transistor is connected to the second terminal of thesecond capacitor, a control terminal of the sixth transistor isconnected to the low level terminal, and an output terminal of the sixthtransistor is connected to the high level terminal.
 16. Theelectrostatic discharge circuit according to claim 15, wherein the firsttransistor is a first N-type transistor, the second transistor is asecond P-type transistor, the third transistor is a third N-typetransistor, the fourth transistor is a fourth P-type transistor, thefifth transistor is a fifth N-type transistor, and the sixth transistoris a sixth P-type transistor.
 17. The electrostatic discharge circuitaccording to claim 15, wherein the first transistor is a first N-typetransistor, the second transistor is a second P-type transistor, thethird transistor is a third P-type transistor, the fourth transistor isa fourth N-type transistor, the fifth transistor is a fifth N-typetransistor, and the sixth transistor is a sixth P-type transistor. 18.An electrostatic discharge circuit, comprising: a first discharge unitcomprising a first N-type transistor and a second P-type transistor,wherein a source of the first N-type transistor is connected to a highlevel terminal, a gate and a drain of the first N-type transistor areconnected together to form a first pole, a gate and a drain of thesecond P-type transistor are connected together to form a second pole,the first pole and the second pole are connected together and connectedto an electrostatic input terminal, and a source of the second P-typetransistor is connected to a low level terminal; a second discharge unitcomprising a third N-type transistor, a first capacitor, and a fifthN-type transistor, wherein a source of the third N-type transistor isconnected to the gate of the first N-type transistor, a drain of thethird N-type transistor is connected to a common terminal, the commonterminal is grounded, a first terminal of the first capacitor isconnected to the electrostatic input terminal, a second terminal of thefirst capacitor is connected to a gate of the third N-type transistor, asource of the fifth N-type transistor is connected to the secondterminal of the first capacitor, a gate of the fifth N-type transistoris connected to the high level terminal, a drain of the fifth N-typetransistor is connected to the low level terminal, and the seconddischarge unit functions to discharge when a positive voltage isapplied; and a third discharge unit comprising a fourth P-typetransistor, a second capacitor and a sixth P-type transistor, wherein asource of the fourth P-type transistor is connected to the gate of thesecond P-type transistor, a drain of the fourth P-type transistor isconnected to the common terminal, the common terminal is grounded, afirst terminal of the second capacitor is connected to the electrostaticinput terminal, a second terminal of the second capacitor is connectedto a gate of the fourth P-type transistor, a source of the sixth P-typetransistor is connected to the second terminal of the second capacitor,a gate of the sixth P-type transistor is connected to the low levelterminal, a drain of the sixth P-type transistor is connected to thehigh level terminal, and the third discharge unit functions to dischargewhen a negative voltage is applied.
 19. The electrostatic dischargecircuit according to claim 18, wherein the second discharge unitcomprises a first electroconductive wire having one end connected to thecommon terminal, and the common terminal is grounded; or the seconddischarge unit comprises a first electroconductive wire having one endconnected to the common terminal, the electrostatic discharge circuit isdisposed on a display panel, and the common terminal is connected to acommon voltage terminal of the display panel.
 20. The electrostaticdischarge circuit according to claim 18, wherein the third dischargeunit comprises a second electroconductive wire having one end connectedto the common terminal, and the common terminal is grounded; or thethird discharge unit comprises a second electroconductive wire havingone end connected to the common terminal, and the common terminal isconnected to a common voltage terminal of the display panel.